 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ? motorola inc., 1995 motorola technical data semiconductor order this document by dsp56005/d rev. 1 dsp56005 advance information 24-bit digital signal processor the dsp56005 is an mpu-style general purpose digital signal processor (dsp), composed of an ef?ient 24-bit digital signal processor core, program and data memories, various peripherals, and support circuitry. the 56000-family-compatible dsp core is fed by a large program ram, two in- dependent data rams, and two data roms with sine and arc-tangent tables. like the dsp56002, the dsp56005 contains a serial communication interface (sci), synchronous serial interface (ssi), parallel host interface (hi), a 24-bit timer/event counter, and on-chip emulation (once ? ) port. features of the dsp56005 include the large on-chip program memory, ?e pulse width modula- tors (pwm), a watchdog timer, and an address decode pin for external peripherals. this combina- tion of features, illustrated in figure 1, makes the dsp56005 a cost-effective, high-performance solution for many dsp and control applications, especially in high-performance motor control, optical disk drives and audio processing. figure 1 dsp56005 block diagram this document contains information on a product under development. motorola reserves the right to change or discontinue this product without notice. address 16 y data memory 256 24 ram 256 24 rom x data memory 256 24 ram 256 24 rom program memory 4608 24 ram 96 24 rom program control unit 24-bit 56000 dsp core once port pll clock gen. 14 pulse width modul. watch- dog timer 1 24-bit timer / event counter 6 sync. serial (ssi) or i/o 3 serial comm. (sci) or i/o 15 host interface (hi) or i/o 16-bit bus 24-bit bus external address bus switch data 24 external data bus switch control 6 bus control data alu 24 24 + 56 ? 56-bit mac two 56-bit accumulators gdb pdb xdb ydb pa b xab ya b interrupt control program decode controller program address generator 5 irq 4 5 internal data bus switch address generation unit (boot) (sine) (arc-tangent) (5)
2 dsp56005 data sheet motorola introduction dsp56005 features digital signal processing core efficient, object code compatible, 24-bit 56000-family dsp engine up to 25 million instructions per second (mips) ?40 ns instruction cycle at 50 mhz up to 150 million operations per second (mops) at 50 mhz executes a 1024-point complex fast fourier transform (fft) in 59,898 clocks highly parallel instruction set with unique dsp addressing modes two 56-bit accumulators including extension byte parallel 24 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles) double precision 48 48-bit multiply with 96-bit result in 6 instruction cycles 56-bit addition/subtraction in 1 instruction cycle fractional arithmetic with support for multiprecision arithmetic hardware support for block-floating point fft hardware nested do loops zero-overhead fast interrupts (2 instruction cycles) four 24-bit internal data buses and three 16-bit internal address buses for simultaneous accesses to one program and two data memories memory on-chip harvard architecture permitting simultaneous accesses to program and two data memories 4608 24-bit on-chip program ram and 96 24-bit bootstrap rom two 256 24-bit on-chip data rams two 256 24-bit on-chip data roms containing sine and arc-tangent tables external memory expansion with 16-bit address and 24-bit data buses bootstrap loading from external data bus, host interface, or serial communications interface peripheral and support circuits byte-wide host interface (hi) with direct memory access (dma) support synchronous serial interface (ssi) to communicate with codecs and synchronous serial devices serial communication interface (sci) for full-duplex asynchronous communications five pulse width modulators (pwm) three with alternate outputs; two with open drain or ttl outputs 9- to 16-bit data width alternate outputs independently selectable as active-high or active-low 24-bit timer/event counter also generates and measures digital waveforms 16-bit watchdog timer dsp56005 features motorola dsp56005 data sheet 3 introduction on-chip peripheral registers memory mapped in data memory space double buffered peripherals up to 25 general purpose i/o pins five external interrupt request pins on-chip emulation (once) port for unobtrusive, processor speed-independent debugging software-programmable, phase-locked loop (pll) based frequency synthesizer for the core clock external peripheral address decode signal miscellaneous features power-saving wait and stop modes fully static, hcmos design for operating frequencies from 50 mhz down to dc 144-pin thin quad flat pack (tqfp) surface-mount package; 20 20 1.4 mm 5 v power supply product documentation more detailed documentation is available describing the dsp56005. the three documents list- ed in table 1 are required for a complete description of the dsp56005 and are necessary to properly design with the part. documentation is available from a local motorola distributor or semiconductor sales of?e, or through a motorola literature distribution center. table 1 additional dsp56005 documentation document name description order number dsp56000 family manual detailed description of the 56000-family architecture and the 24-bit core processor and instruction set dsp56kfamum/ad dsp56005 user s manual detailed description of memory, peripherals, and interfaces dsp56005um/ad dsp56005 data sheet electrical and timing specifications, and pin and package descriptions dsp56005/d dsp56005 features product documentation 4 dsp56005 data sheet motorola introduction related documentation table 2 lists additional documentation relevant to the dsp56005. table 2 dsp56005 related documentation document name description order number motorola s 16-, 24-, and 32-bit digital signal processing families overview of all of the dsp product fami- lies. br1105/d digital sine-wave synthesis application report. uses the dsp56001 look-up table. apr1/d digital stereo 10-band graphic equalizer application report. includes code and circuitry; features the dsp56001. apr2/d fractional and integer arithmetic application report. includes code. apr3/d implementation of fast fourier transforms application report. comprehensive fft algorithms and code for dsp56001, dsp56156, and dsp96002. apr4/d implementation of pid controllers application report. pwm using the sci timer and three phase output using mod- ulo addressing. apr5/d convolutional encoding and vit- erbi decoding with a v.32 modem trellis example application report. theory and code; fea- tures the dsp56001. apr6/d implementing iir/fir filters application report. comprehensive exam- ple using the dsp56001. apr7/d principles of sigma-delta modula- tion for a-to-d converters application report. features the dsp56adc16; improving resolution with half-band ?ters apr8/d full-duplex 32-kbit/s ccitt adpcm speech coding application report. features the dsp56001 apr9/d dsp56001 interface techniques and examples application report. interfaces for pseudo static ram, dynamic ram, isa bus, host apr11/d twin codec expansion board for the dsp56000 ads application report. circuit, code, fir ?ter design for two voice band codecs con- necting to the ssi apr12/d conference bridging in the digital telecommunications environment application report. theory and code; fea- tures the dsp56001/002 apr14/d implementation of adaptive controllers application report. adaptive control using reference models; generalized predictive control; includes code apr15/d product documentation motorola dsp56005 data sheet 5 introduction calculating timing requirements of external sram application report. determination of sram speed for optimum performance apr16/d pc media hardware reference design version 4.0 application report. audio, telephony, and entertainment board design apr19/d low cost controller for dsp56001 application report. circuit and code to connect two dsp56001s to an mc68008 apr402/d g.722 audio processing application report. theory and code using sb-adpcm apr404/d minimal logic dram interface application report. 1m x 480 ns dram, 1 pal, code apr405/d logarithmic/linear conversion routines application report. m -law and a-law com- panding routines for pcm mono-circuits ane408/d dr. bub bulletin board flyer. motorola s electronic bulletin board where free dsp software is available br297/d dsp development tools overview of motorola's hardware and soft- ware development tools dsptoolsp/d third party compendium brochures from companies selling hard- ware and software that supports motorola dsps dsp3rdptypak/d university support program flyer. motorola s program supporting uni- versities in dsp research and education br382/d technical training schedule technical training schedule br348/d real time signal processing applications with motorola s dsp56000 family textbook by mohamed el-sharkawy; 398+ pages. (this is a charge item.) prentice-hall, 1990; isbn 0-13-767138-5 table 2 dsp56005 related documentation (continued) document name description order number product documentation 6 dsp56005 data sheet motorola introduction data sheet contents this data sheet contains: pin descriptions . . . . . . . . . . . . . . . . . . . 9 electrical specifications . . . . . . . . . . . . . 21 pin-out and package. . . . . . . . . . . . . . . . left design considerations . . . . . . . . . . . . . . 77 ordering information. . . . . . . . . . . . . . . 87 data sheet conventions this data sheet uses the following conventions: overbars are used to indicate a signal that is active when pulled to ground (see table 3) e.g. the hreq pin is active when pulled to ground. therefore, references to the hreq pin will always have an overbar. the word ?ssert?(see table 3) means that a high true (active high) signal is pulled high to v cc or that a low true (active low) signal is pulled low to ground. the word ?eassert?(see table 3) means that a high true signal is pulled low to ground or that a low true signal is pulled high to v cc . table 3 high true / low true signal conventions signal/symbol logic state signal state voltage pin true asserted ground pin false deasserted v cc pin true asserted v cc pin false deasserted ground notes: 1. pin is a generic term for any pin on the chip. 2. ground is an acceptable low voltage level. see the dc electrical specifications for the range of acceptable low voltage levels (typically a ttl logic low). 3. v cc is an acceptable high voltage level. see the dc electrical specifications for the range of acceptable high voltage levels (typically a ttl logic high). contents conventions motorola dsp56005 data sheet 7 introduction pin groupings the input and output signals of the dsp56005 are organized into function groups as shown in table 4 and as illustrated in figure 2. pin groupings 8 dsp56005 data sheet motorola introduction a0-a15 d0-d23 ds ps rd wr x/y gndd v ccd gnda v cca gndc v ccc gndq v ccq extal xtal reset moda/irqa modb/irqb modc/nmi h0-h7 ha0-ha2 hr/w hen hreq hack gndh v cch rxd txd sclk v ccs gnds sc0-sc2 sck srd std dsck/os1 dsi/os0 dso dr interrupt/ mode control dsp56005 host serial synchronous pwap0 - pwap2 pwan0 - pwan2 ckout pulse width pwaclk pwac0 - pwac2 v ccck gndck tio timer/ event irqc irqd clock v ccp gndp pcap phase-locked pinit pwb0 , pwb1 pwbc pwbclk v ccw gndw counter oscillator extp modulator a (pwma0-2) pulse width modulator b (pwmb0-1) interface (hi) communication interface (sci) serial interface (ssi) loop (pll) on-chip emulator (once) port external bus control external address bus external data bus figure 2 dsp56005 pin functions pin functions motorola dsp56005 data sheet 9 pin descriptions pin descriptions the dsp56005 is available in a 144 tqfp. the pins are organized into the functional groups indicat- ed in table 4. the signals are discussed in the paragraphs that follow. all unused inputs should have pull-up resistors for two reasons: 1. floating inputs draw excessive power 2. floating input can cause erroneous opera- tion for example, during reset, all signals are three-stated. a pull-up resistor in the 50 k w range should be suf?ient. also, for future enhancements, all reserved ?o connect?(nc), pins should be left unconnected. address and data bus the port a address and data bus signals control the access to external memory. these signals are three-stated during reset unless noted otherwise, and may require pull-up resistors to minimize power consumption and to prevent erroneous operation. a0?15 (address bus) ?three-state, out- puts. a0-a15 specify the address for external program and data memory ac- cesses. if there is no external bus activi- ty, a0-a15 remain at their previous values. a0-a15 are three-stated during hardware reset. d0?23 (data bus) ?three-state, bidirec- tional input/outputs. data for external memory i/o is presented on d0-d23. if there is no external bus activity, d0-d23 are three-stated. d0-d23 are also three-stated during hardware reset. bus control the bus control signals are three-stated during re- set and may require pull-up resistors to prevent erroneous operation. ps (program memory select) three-state, active low output this output is asserted only when external program memory is referenced (see ta- ble 5). ps timing is the same as the a0-a15 address lines. if the external bus is not used during an instruction cycle, ps is driven high. ps is three-stat- ed during hardware reset. ds (data memory select) ?three-state, active low output this three-state out- put is asserted only when external data memory is referenced (see table 5). if the external bus is not used during an instruction cycle, ds is driven high. ds is three-stated during hardware re- set. x/y (x/y select) ?three-state output. this three-state output selects which external data memory space (x or y) is referenced by ds (see table 5). x/y is three-stated during hardware reset. rd (read enable) ?three-state, active low output. this output is asserted during external memory read cycles. when rd is asserted, the data bus pins d0-d23 become inputs, and an external device is enabled onto the data bus. when rd is deasserted, the external data is latched inside the dsp. when rd is asserted, it qualifies the a0-a15, ps and ds pins. rd can be connected directly to the oe pin of a static ram or rom. rd is three-stated during hardware reset. address and data bus bus control pin descriptions 10 dsp56005 data sheet motorola wr (write enable) ?three-state, active low output. this output is asserted during external memory write cycles. when wr is asserted, the data bus pins d0-d23 become outputs, and the dsp puts data on the bus. when wr is deas- serted, the external data is latched in- side the external device. when wr is asserted, it qualifies the a0-a15, ps and ds pins. wr can be connected di- rectly to the we pin of a static ram. wr is three-stated during hardware re- set. extp (external peripheral) ?active low output. the extp pin is an output as- serted whenever the external y memo- ry i/o space (y:$ffc0-$ffff) is accessed. this signal simplifies gener- ating peripheral enable signals. no ad- ditional circuitry is needed if only one external peripheral is used. for most applications, no more than one decode chip is needed and, as a result, decode delays are minimized. using the y memory i/o space allows the movep instruction to be used to send and to re- ceive data. using the movep instruc- tion may allow the entire i/o routine to fit in a fast interrupt. extp is three-stated during hardware reset. table 5 program and data memory select encoding ps ds x/y external memory reference 1 1 1 no activity 1 0 1 x data memory on data bus 1 0 0 y data memory on data bus 0 1 1 program memory on data bus (not an exception) 0 1 0 external exception fetch: vector or vector +1 (development mode only) 0 0 x reserved 1 1 0 reserved host interface the following paragraphs discuss the host inter- face signals, which provide a convenient connec- tion to another processor. h0?7 (host data bus) ?bidirectional. this bidirectional data bus is used to transfer data between the host processor and the dsp. this bus is an input unless enabled by a host processor read. it is high im- pedance when hen is deasserted. h0-h7 may be programmed as port b general purpose parallel i/o pins called pb0-pb7 when the host interface (hi) is not being used. these pins are config- ured as gpio input pins during hard- ware reset. ha0?a2 (host address) ?input. * these in- puts provide the address selection for each hi register and must be stable when hen is asserted. ha0-ha2 may be programmed as port b general pur- pose parallel i/o pins called pb8-pb10 when the hi is not being used. these pins are configured as gpio input pins during hardware reset. *note that these pins can be inputs or outputs when programmed as general purpose i/o. bus control hi motorola dsp56005 data sheet 11 pin descriptions deasserted when the enabled request is cleared or masked, dma hack is as- serted, or the dsp is reset. hreq may be programmed as a general purpose i/o pin (not open-drain) called pb13 when the hi is not being used. this pin is configured as a gpio input pin dur- ing hardware reset. hack (host acknowledge) ?active low in- put. * this input has two functions: to provide a host acknowledge signal for dma transfers to control handshaking and to provide a host interrupt acknowledge compatible with mc68000 family processors if programmed as a host acknowledge signal, hack may be used as a data strobe for hi dma data transfers. if programmed as an mc68000 host in- terrupt acknowledge, hack enables the hi interrupt vector register (ivr) onto the host data bus h0-h7 if the host request hreq output is asserted. in this case, all other hi control pins are ignored and the hi state is not affected. hack may be programmed as a gen- eral purpose i/o pin called pb14 when the hi is not being used. this pin is configured as a gpio input pin during hardware reset. note: hack should always be pulled high when not in use. serial communication interface (sci) rxd (receive data) ?input. * this input receives byte-oriented data and trans- fers the data to the sci receive shift reg- ister. input data is sampled on the hr/w (host read/write) ?input. * this in- put selects the direction of data transfer for each host processor access. if hr/w is high and hen is asserted, h0-h7 are outputs, and dsp data is transferred to the host processor. if hr/w is low and hen is asserted, h0-h7 are inputs and host data is transferred to the dsp when hen is deasserted. when hen is as- serted, hr/w must be stable. hr/w may be programmed as a general pur- pose i/o pin called pb11 when the hi is not being used. this pin is config- ured as a gpio input pin during hard- ware reset. hen (host enable) ?active low input. * this input enables a data transfer on the host data bus. when hen is assert- ed and hr/w is high, h0-h7 becomes an output and dsp data may be latched by the host processor. when hen is as- serted and hr/w is low, h0-h7 is an input and host data is latched inside the dsp when hen is deasserted. nor- mally a chip select signal derived from host address decoding and an enable clock is connected to the host enable. hen may be programmed as a general purpose i/o pin called pb12 when the hi is not being used. this pin is config- ured as a gpio input pin during hard- ware reset. hreq (host request) ?active low output. * this open-drain output signal is used by the dsp to request service from the host processor. hreq may be connect- ed to a host processor interrupt request pin, a dma controller transfer request pin, or a control input to external cir- cuitry. hreq is asserted when an en- abled request occurs in the hi. hreq is *note that these pins can be inputs or outputs when programmed as general-purpose i/o. hi sci pin descriptions 12 dsp56005 data sheet motorola positive or the negative edge of the re- ceive clock, depending on how the sci control register is programmed. rxd may be programmed as a general-pur- pose i/o pin called pc0 when it is not being used as an sci pin. this pin is configured as a gpio input pin during hardware reset. txd (transmit data) ?output. * this out- put transmits serial data from the sci transmit shift register. data changes on the negative edge of the transmit clock. this output is stable on the positive or the negative edge of the transmit clock, depending on how the sci control reg- ister is programmed. txd may be pro- grammed as a general-purpose i/o pin called pc1 when the sci txd function is not being used. this pin is config- ured as a gpio input pin during hard- ware reset. sclk (sci serial clock) ?bidirectional. this bidirectional pin provides an in- put or output clock from which the transmit and/or receive baud rate is derived in the asynchronous mode, and from which data is transferred in the synchronous mode. sclk may be programmed as a general-purpose i/o pin called pc2 when the sci sclk function is not being used. this pin is configured as a gpio input pin during hardware reset. synchronous serial interface (ssi) sc0 (serial control 0) ?bidirectional. this bidirectional pin? function is de- *these pins can be input or output when pro- grammed as general-purpose i/o. termined by whether the ssi is in syn- chronous or asynchronous mode. in synchronous mode, this pin is used for serial flag i/o. in asynchronous mode, this pin receives clock i/o. sc0 and sc1 are independent serial i/o flags but may be used together for multiple serial device selection. sc0 may be pro- grammed as a general-purpose i/o pin called pc3 when the ssi sc0 function is not used. this pin is configured as a gpio input pin during hardware reset. sc1 (serial control 1) ?bidirectional. the ssi uses this bidirectional pin to control flag or frame synchronization. this pin? function is determined by whether the ssi is in synchronous or asynchronous mode. in asynchronous mode, this pin is frame sync i/o. for synchronous mode with continuous clock, this pin is serial flag sc1 and op- erates like the sc0. sc0 and sc1 are in- dependent serial i/o flags but may be used together for multiple serial device selection. sc1 may be programmed as a general-purpose i/o pin called pc4 when the ssi sc1 function is not being used. this pin is configured as a gpio input pin during hardware reset. sc2 (serial control 2) ?bidirectional. the ssi uses this bidirectional pin to control frame synchronization only. as with sc0 and sc1, its function is de- fined by the ssi operating mode. sc2 may be programmed as a general-pur- pose i/o pin called pc5 when the ssi sc2 function is not being used. this pin is configured as a gpio input pin dur- ing hardware reset. sck (ssi serial clock) ?bidirectional. this bidirectional pin provides the seri- al bit rate clock for the ssi when only one clock is being used. sck may be sci ssi motorola dsp56005 data sheet 13 pin descriptions programmed as a general-purpose i/o pin called pc6 when it is not needed as an ssi pin. this pin is configured as a gpio input pin during hardware reset. srd (ssi receive data) ?input. * this in- put pin receives serial data into the ssi receive shift register. srd may be pro- grammed as a general-purpose i/o pin called pc7 when the srd function is not being used. this pin is configured as a gpio input pin during hardware reset. std (ssi transmit data) ?output. * this output pin transmits serial data from the ssi transmit shift register. std may be programmed as a general-purpose i/o pin called pc8 when the std func- tion is not being used. this pin is con- figured as a gpio input pin during hardware reset. timer/event counter tio (timer/event counter input/output) ?bidirectional. the tio pin provides an interface to the timer/event counter module. when the module functions as an external event counter or is used to measure an external pulse width/signal period, the tio is used as an input. when the module functions as a timer, the tio is an output and the signal on the tio pin is the timer pulse. when not used by the timer module, the tio can act as a general purpose i/o pin. reset disables the tio pin and causes it to be three-stated. pulse width modulator a (pwma) pulse width modulator a is a set of three 16-bit signed two? complement fractional data pulse width modulators and has 10 dedicated external pins. these pulse width modulators are indepen- dent of the pwmb modulators. pwap0 - pwap2 (pulse width modulator a positive) ?output. these three pins are the positive outputs for the three pwma modulators (pwma0, pwma1, and pwma2). when a posi- tive two? complement number is load- ed in one of the three pwma count registers, an output signal will be gen- erated on the respective pin (e.g., load- ing pwacr0 with a positive two? complement number will generate an output on pwap0). when a negative two? complement number is loaded in a pwma count register, pwap0-pwap2 will be at its inactive logic level (as defined by the polarity bits in the pwma con- trol/status register 1). these pins are driven at their inactive logic level (as defined by the polarity bits in the con- trol/status register 1) when the indi- vidual pwm modulator (pwma0, pwma1, or pwma2) is not enabled. during hardware reset, these pins are driven to a high logic level. pwan0 - pwan2 (pulse width modulator a negative) ?output. these three pins are the negative outputs for the three pwma modulators (pwma0, pwma1, and pwma2). when a nega- tive two? complement number is load- ed in one of the three pwma count registers, an output signal will be gen- erated on the respective pin (e.g. load- ing pwacr0 with a negative two? ssi timer * these pins can be input or output when programmed as general purpose i/o. pwma pin descriptions 14 dsp56005 data sheet motorola complement number will generate an output on pwan0). when a positive two? complement number is loaded in a pwma count register, the n-output (pwan0- pwan2) of this pwma block will be at its inactive logic level (as defined by the polarity bits in the pwma con- trol/status register 1). these pins are driven at their inactive logic level (as defined by the polarity bits in the con- trol/status register 1) when the indi- vidual pwm modulator (pwma0, pwma1, or pwma2) is not enabled. during hardware reset, these pins are driven to a high logic level. pwac0 - pwac2 (pulse width modulator a carrier) ?input. these three pins are inputs that provide the external carrier signals for the three pwmas (pwma0, pwma1 and pwma2). when the car- rier source for the respective pwma block is programmed to be external, the modulator starts operation at each rising edge of its carrier signal. while a pwma block is either disabled, or is enabled and programmed to operate with the internal carrier, its respective internal input buffer is disconnected from the pin and no external pull-up is necessary. pwaclk (pulse width modulator a clock) input. this input increments the pres- caler which connects to the three pwma blocks and increments the counter in each these blocks. if all of the pwma blocks are either disabled, or are programmed to use the internal clock, the internal input buffer is dis- connected from the pin and no external pull-up is necessary. pulse width modulator b (pwmb) pulse width modulator b is a pair 16-bit positive fractional data pulse width modulators and has four dedicated external pins. these two pulse width modulators are independent of the pwma modulators. pwbc (pulse width modulator b carrier) input. this pin is an input that pro- vides the external carrier signals for the two pwmb blocks (pwmb0 and pwmb1). when the carrier source for these blocks is programmed to be ex- ternal, these blocks start operation at each rising edge of this signal. while a pwmb block is either disabled, or is enabled and programmed to operate with the internal carrier, its respective internal input buffer is disconnected from the pin and no external pull-up is necessary. pwb0 -pwb1 (pulse width modulator b out- put) ?active low output. these two pins are the outputs for pulse width modulators pwmb0 and pwmb1. these pins are either open drain or driven at ttl levels depending on the programming of pwbcsr1 bit 14 (wbr0). these pins are also in the high-impedance state or in a high logic state (depending on the value of the bit wbo in pwbcsr1) when pwmb0 and pwmb1 are disabled. during hard- ware reset, these pins are in the high-impedance state. pwbclk (pulse width modulator b clock) input. this input increments the pres- caler which increments the counter connected to the two pwmb blocks. while both pwmb blocks are disabled, the internal input buffer is disconnect- ed from the pin and no external pull-up pwma pwmb motorola dsp56005 data sheet 15 pin descriptions is necessary. while the pwmb blocks are programmed to use the internal clock, the internal input buffer is dis- connected from the pin and no external pull-up is necessary. on-chip emulation (once ) port the following paragraphs describe the pins asso- ciated with the once port controller and its serial interface. dsi/os0 (debug serial input/chip status 0) bidirectional. the dsi/os0 pin, when an input, is the pin through which seri- al data or commands are provided to the once port controller. the data re- ceived on the dsi pin will be recog- nized only when the dsp has entered the debug mode of operation. data must have valid ttl logic levels before the serial clock falling edge. data is al- ways shifted into the once serial port most significant bit (msb) first. when the dsp is not in the debug mode, the dsi/os0 pin provides information about the chip status if it is an output and used in conjunction with the os1 pin. when switching from output to input, the pin is three-stated. during hard- ware reset, this pin is defined as an out- put and it is driven low. note: to avoid possible glitches, an external pull-down resistor should be attached to this pin. dsck/os1(debug serial clock/chip status 1) ?bidirectional. the dsck/os1 pin, when an input, is the pin through which the serial clock is supplied to the once port. the serial clock provides pulses required to shift data into and out of the once serial port. data is clocked into the once port on the fall- ing edge and is clocked out of the once serial port on the rising edge. if the dsck/os1 pin is an output and used in conjunction with the os0 pin, it provides information about the chip status when the dsp is not in the debug mode. the debug serial clock frequen- cy must be no greater than 1 / 8 of the processor clock frequency. the pin is three-stated when it is changing from input to output. during hardware re- set, this pin is defined as an output and is driven low. note: to avoid possible glitches, an external pull-down resistor should be attached to this pin. dso (debug serial output) ?output. the debug serial output provides the data contained in one of the once port con- troller registers as specified by the last command received from the command controller. the most significant bit (msb) of the data word is always shift- ed out of the once serial port first. data is clocked out of the once port serial port on the rising edge of dsck. the dso pin also provides acknowl- edge pulses to the external command controller. when the chip enters the de- bug mode, the dso pin will be pulsed low to indicate (acknowledge) that the once port is waiting for commands. after receiving a read command, the dso pin will be pulsed low to indicate that the requested data is available and the once port serial port is ready to re- ceive clock pulses in order to deliver the data. after receiving a write com- mand, the dso pin will be pulsed low to indicate that the once serial port is ready to receive the data to be written; pwmb once port pin descriptions 16 dsp56005 data sheet motorola after the data is written, another ac- knowledge pulse will be provided. during hardware reset and when idle, the dso pin is held high. dr (debug request) ?active low input. the debug request input provides a means of entering the debug mode of operation. this pin, when asserted, will cause the dsp to finish the current in- struction being executed, to save the in- struction pipeline information, to enter the debug mode, and to wait for com- mands to be entered from the debug se- rial input line. while the dsp is in the debug mode, the user can reset the once port controller by asserting dr , waiting for an acknowledge from dso, and then deasserting dr . it may be necessary to reset the once port con- troller in cases where synchronization between the once port controller and external circuitry is lost. asserting dr when the dsp is in the wait or the stop state, and keeping it asserted until an acknowledge pulse in the dsp is pro- duced, sends the dsp into the debug mode. after receiving the acknowl- edge, dr must be deasserted before sending the first once port command. power and ground note: to avoid possible glitches, an external pull-up resister should be at- tached to this pin the power and ground pins are presented in the following paragraphs. there are ten sets of power and ground pins (see table 25). in accordance with good engineering practice, v cc should be bypassed to ground (as needed) by a 0.1 m f capac- itor located as close as possible to the chip pack- age. the two circuits where this bypassing is most important are the pll and the core processor in- ternal logic circuits. power these v cc pins provide power to the circuits list- ed in table 25, ?sp56005 power supply pins,? on page 77. the voltage should be well regulated and the pin should be provided with an extreme- ly low impedance path to the power rail. v ccp (pll circuit power) . this pin supplies a quiet power source to the phase-locked loop (pll) to provide greater frequency stability. the voltage should be well regulated and the pin should be provided with an extremely low impedance path to the power rail. v ccp should be bypassed to gndp by a 0.1 m f capacitor located as close as possible to the chip package. ground these pins provide grounds for the circuits listed in table 25, ?sp56005 power supply pins,?on page 77. the pins should be provided with an ex- tremely low impedance path to ground. gndp (pll circuit ground). this pin sup- plies a quiet ground source to the pll to provide greater frequency stability. the pin should be provided with an ex- tremely low impedance path to ground. v ccp should be bypassed to gndp by a 0.1 m f capacitor located as close as possible to the chip package. interrupt and mode control the interrupt and mode control pins select the chip? operating mode as it comes out of hard- ware reset and receive interrupt requests from ex- ternal sources after reset. once port power and ground motorola dsp56005 data sheet 17 pin descriptions moda/irqa (mode select a/external interrupt request a) ?input. this input pin has three functions: to work with the modb and modc pins to select the chip? initial operating mode to allow an external device to request a dsp interrupt after internal synchronization to turn on the internal clock generator when the dsp in the stop processing state, causing the chip to resume processing moda is read and internally latched in the dsp when the processor exits the reset state. moda, modb, and modc select the initial chip operating mode. several clock cycles after leaving the re- set state, the moda pin changes to the external interrupt request irqa . the chip operating mode can be changed by software after reset. the irqa input is a synchronized ex- ternal interrupt request. it may be pro- grammed to be level sensitive or negative edge triggered. when the sig- nal is edge triggered, triggering occurs at a voltage level and is not directly re- lated to the fall time of the interrupt signal. however, as the fall time of the interrupt signal increases, the probabil- ity that noise on irqa will generate multiple interrupts also increases. while the dsp is in the stop processing state, asserting irqa gates on the oscil- lator and, after a clock stabilization de- lay, enables clocks to the processor and peripherals. hardware reset causes this input to act as moda. modb/irqb (mode select b/external interrupt request b) ?input. this input pin has two functions: to work with the moda and modc pins to select the chip? initial operating mode to allow an external device to request a dsp interrupt after internal synchronization modb is read and internally latched in the dsp when the processor exits the re- set state. moda, modb, and modc se- lect the initial chip operating mode. several clock cycles after leaving the re- set state, the modb pin changes to the external interrupt request irqb . the chip operating mode can be changed by software after reset. the irqb input is a synchronized exter- nal interrupt request. it may be pro- grammed to be level sensitive or negative edge triggered. when the signal is edge triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. however, as the fall time of the interrupt signal increases, the probability that noise on irqb will generate multiple in- terrupts also increases. hardware reset causes this input to act as modb. modc/nmi (mode select c/non-maskable inter- rupt request) ?edge triggered input. this input pin has two functions: to work with the moda and modb pins to select the chip? initial operating mode to allow an external device to request a dsp interrupt after internal synchronization interrupt and mode control pin descriptions 18 dsp56005 data sheet motorola modc is read and internally latched in the dsp when the processor exits the reset state. moda, modb, and modc select the initial chip operating mode. several clock cycles after leaving the re- set state, the modc pin changes to the non-maskable interrupt request, nmi . the chip operating mode can be changed by software after reset. the nmi input is a negative-edge trig- gered external interrupt request. this is a level 3 interrupt that can not be masked out. triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. however, as the fall time of the inter- rupt signal increases, the probability that noise on nmi will generate multi- ple interrupts also increases. hardware reset causes this input to act as modc. irqc (external interrupt request c) edge triggered input. this negative edge triggered input allows an external device to request a dsp interrupt after internal synchronization. triggering occurs at a voltage level and is not di- rectly related to the fall time of the in- terrupt signal. however, as the fall time of the interrupt signal increases, the probability that noise on irqc will generate multiple interrupts also in- creases. irqd (external interrupt request d) edge triggered input. this negative edge triggered input allows an external device to request a dsp interrupt after internal synchronization. triggering occurs at a voltage level and is not di- rectly related to the fall time of the in- terrupt signal. however, as the fall time of the interrupt signal increases, the probability that noise on irqd will generate multiple interrupts also in- creases. reset (reset) ?input. this input is a direct hardware reset of the processor. when reset is asserted, the dsp is initialized and placed in the reset state. a schmitt trigger input is used for noise immunity. when the reset pin is deasserted, the ini- tial chip operating mode is latched from the moda, modb, and modc pins. the chip also samples the pinit pin and writes its status into the pen bit of the pll control register. when the chip comes out of the reset state, deas- sertion occurs at a voltage level and is not directly related to the rise time of the reset signal. however, the proba- bility that noise on reset will generate multiple resets increases with increas- ing rise time of the reset signal. clock, oscillator, and pll the following pins are dedicated to the pll, clock, and oscillator operation. ckout (output clock) ?output. this output pin provides a 50% duty cycle output clock synchronized to the internal pro- cessor clock when the pll is enabled and locked. when the pll is disabled, the output clock at ckout is derived from, and has the same frequency and duty cycle as, extal. note: if the pll is enabled and the multiplication factor is less than or equal to 4, then ckout is synchro- nized to extal. (for information on the dsp56005? pll multiplication fac- tor, see section 3.5 ?dsp56005 phase-locked loop configuration in the dsp56005 user? manual . interrupt and mode control clock, oscillator, and pll motorola dsp56005 data sheet 19 pin descriptions extal (external clock/crystal) ?input. this pin may be used in one of two ways: driven from an external clock interface the internal crystal oscillator input to an external crystal circuit if the pll is enabled, this pin is inter- nally connected to the on-chip pll. the pll can multiply the frequency on the extal pin to generate the internal dsp clock. the pll output is divided by two to produce a four-phase instruc- tion cycle clock, with the minimum in- struction time being two pll output clock periods. if the pll is disabled, extal is divided by two to produce the four-phase instruction cycle clock. xtal (crystal) ?output. this output con- nects the internal crystal oscillator out- put to an external crystal. if an external clock is used, xtal should not be con- nected. it may be disabled through software control using the xtld bit in the pll control register. pcap (pll filter capacitor) ?input. this input is used to connect a high quality external capacitor needed for the pll filter. the capacitor should be as close as possible to the chip with heavy, short traces connecting one terminal of the capacitor to pcap and the other terminal to v ccp . pinit (pll initialization) ?input. during the assertion of hardware reset, the val- ue at the pinit input pin is written into the pen bit of the pll control register. when high, the pen bit enables the pll by causing it to derive the internal clocks from the pll voltage controlled oscillator output. when the bit is clear, the pll is disabled and the chip? inter- nal clocks are derived from the clock connected to the extal pin. after hardware reset is deasserted, the pinit pin is ignored. clock, oscillator, and pll pin descriptions 20 dsp56005 data sheet motorola motorola dsp56005 data sheet 21 electrical characteristics electrical specifications the preliminary dc/ac electrical speci?ations are generated from design simulations. these speci?ations may not be fully tested or guaranteed at this early stage of the product life cycle. finalized speci?ations will be published after complete characterization and device quali?ations have been completed. the dsp56005 is fabricated in high density cmos with ttl compatible inputs and outputs. note: this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any volt- ages higher than maximum-rated voltages to this high-impedance circuit. reliability of opera- tion is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either gnd or v cc ). table 6 maximum ratings (gnd = 0vdc) rating symbol value unit supply voltage v cc -0.3 to +7.0 v all input voltages v in gnd - 0.5 to v cc + 0.5 v current drain per pin excluding v cc and gnd i10ma operating temperature range t j -40 to +105 c storage temperature t stg -55 to +150 c table 7 thermal characteristics of the tqfp package thermal resistance symbol value rating junction to ambient q ja 49 c/w junction to case q jc 8 c/w 22 dsp56005 data sheet motorola dc electrical characteristics dc electrical characteristics v cc = 5.0 vdc 10%; t j = -40 to +105 c notes: 1. in order to obtain these results, all inputs must be terminated (i.e., not allowed to float). 2. periodically sampled and not 100% tested 3. power consumption in the design considerations section describes how to calculate the external supply current. 4. values given are for pll enabled. 5. values given are for ckout enables. table 8 dc electrical characteristics characteristics symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v input high voltage ?except extal, reset , moda, modb, modc ?extal ?reset ?moda, modb, modc v ih v ihc v ihr v ihm 2.0 4.0 2.5 3.5 v cc v cc v cc v cc v v v v input low voltage ?except extal, moda, modb, modc ?extal ?moda, modb, modc v il v ilc v ilm -0.5 -0.5 -0.5 0.8 0.6 2.0 v v v input leakage current extal, reset , moda/irqa , modb/irqb , modc/nmi i in -1 1 m a three-state (off-state) input current (@ 2.4v / 0.4v) i tsi -10 10 m a output high voltage (i oh = -0.4 ma) v oh 2.4 v output low voltage (i ol = 3.2 ma; hreq i ol = 6.7 ma, txd i ol = 6.7 ma) v ol 0.4 v internal supply current 5.5 v, 50 mhz (see note 3) in wait mode (see note 1) in stop mode (see note 1) i cci i ccw i ccs 125 25 2 tbd tbd tbd ma ma m a pll supply current (see note 4) tbd tbd ma clockout supply current (see note 5) tbd tbd ma input capacitance (see note 2) c in ?0 pf motorola dsp56005 data sheet 23 ac electrical characteristics ac electrical characteristics the timing waveforms in the ac electrical characteristics are tested with a v il maximum of 0.5v and a v ih minimum of 2.4v for all pins, except extal, reset , moda, modb, and modc. these ?e pins are tested using the input levels set forth in dc electrical character- istics . ac timing speci?ations which are referenced to a device input signal are measured in production with respect to the 50% point of the respective input signal? transition. dsp56005 output levels are measured on the production test machine with v ol and v oh reference levels set at 0.8v and 2.0v respectively. internal clocks for each occurrence of t h , t l , t c or i cyc substitute with the numbers given in table 9: notes: 1. the ??in et h , et l , and et c means external. 2. mf is the pctl multiplication factor bits (mf0 - mf11). df is the pctl division factor bits (df0 - df3). table 9 internal clocks characteristics symbol expression internal operation frequency f internal clock high period t h - with pll disabled et h (see note 1) - with pll enabled and mf 4 (min) 0.48 x et c x df/mf (max) 0.52 x et c x df/mf (see note 2) - with pll enabled and mf > 4 (min) 0.467 x et c x df/mf (max) 0.533 x et c x df/mf internal clock low period t l - with pll disabled et l (see note 1) - with pll enabled and mf 4 (min) 0.48 x et c x df/mf (max) 0.52 x et c x df/mf - with pll enabled and mf > 4 (min) 0.467 x et c x df/mf (max) 0.533 x et c x df/mf internal clock cycle time t c et c x df/mf (see note 1) instruction cycle time i cyc 2 x t c internal clocks 24 dsp56005 data sheet motorola ac electrical characteristics clock the dsp56005 system clock may be derived from the on-chip crystal oscillator as shown in figure 3, or it may be externally supplied. an externally supplied square wave voltage source should be connected to extal, leaving xtal physically unconnected (see figure 4) to the board or socket. the rise and fall time of this external clock should be 3 ns maximum. when using a crystal to provide a clock input, the frequency must be greater than 500 khz. this restriction does not apply when providing an external clock to the extal pin. figure 3 crystal oscillator circuits suggested component values r = 680 k w 10% c = 20 pf 20% xtal1 c c r fundamental frequency crystal oscillator 3 rd overtone crystal oscillator suggested component values r1 = 470 k w 10% r2 = 330 w 10% c1 = 0.1 m f 20% c2 = 26 pf 20% c3 = 20 pf 10% l1 = 2.37 m h 10% xtal = 50 mhz, at cut, 20 pf load, 50 w max series resistance xtal extal r1 c2 c3 xtal1* l1 c1 r2 extal xtal notes: 1. the suggested crystal source is icm, # 433163 - 4.00 (4 mhz fundamental, 20 pf load) 2. to reduce system cost, a ceramic resonator may be used instead of the crystal. suggested source: murata-erie #cst4.00mgw040 (4 mhz fundamental) notes: 1. *3 rd overtone crystal. 2. the suggested crystal source is icm, # 471163 - 50.00 (50 mhz 3 rd overtone, 20 pf load). 3. r2 limits crystal current. 4. reference benjamin parzen, the design of crystal and other harmonic oscillators , john wiley & sons, 1983. clock motorola dsp56005 data sheet 25 ac electrical characteristics figure 4 external clock timing note: external clock input high and external clock input low are measured at 50% of the input transition. extal v ilc v ihc midpoint 1 2 3 4 note: the midpoint is v ilc + 0.5 (v ihc - v ilc ). et h et l et c table 10 clock operation num characteristics symbol 50 mhz unit min max frequency of operation (extal pin) f 0 50 mhz 1 clock input high (see note) ?with pll disabled (46.7% - 53.3% duty cycle) ?with pll enabled (42.5% - 57.5% duty cycle) et h 9.34 8.5 235500 ns ns 2 clock input low (see note) ?with pll disabled (46.7% - 53.3% duty cycle) ?with pll enabled (42.5% - 57.5% duty cycle) et l 9.34 8.5 235500 ns ns 3 clock cycle time ?with pll disabled ?with pll enabled et c 20 20 409600 ns ns 4 instruction cycle time = i cyc = 2 ? t c (see note) ?with pll disabled ?with pll enabled i cyc 40 40 8192 00 ns ns clock 26 dsp56005 data sheet motorola ac electrical characteristics phase-locked loop (pll) notes: 1. the ??in e f , et h , et l , and et c means external. 2. mf is the pctl multiplication factor bits (mf0 - mf11). df is the pctl division factor bits (df0 - df3). 3. the maximum vco frequency is limited to the internal operation frequency. 4. cpcap is the value of the pll capacitor (connected between pcap pin and v ccp ) for mf=1. the recommended value for cpcap is 400 pf for mf 4 and 540 pf for mf > 4. table 11 phase-locked loop characteristics characteristics expression min max unit vco frequency when pll enabled mf x e f (see notes 1,2) 10 f (see note 3) mhz pll external capacitor (pcap pin to v ccp ) mf ? cpcap (see note 4) @ mf < 4 @ mf > 4 mf 340 mf 380 mf 480 mf ? 970 pf pll motorola dsp56005 data sheet 27 ac electrical characteristics reset, stop, mode select, and interrupt timing v cc = 5.0 vdc 10%, t j = -40 to +105 c, c l = 50 pf + 2 ttl loads ws = number of wait states (1 ws = t c ) programmed into external bus access using bcr (ws = 0 - 15) table 12 reset, stop, mode select, and interrupt timing num characteristics 50 mhz unit min max 9 delay from reset assertion to address high impedance (periodically sampled and not 100% tested) ?6ns 10 minimum stabilization duration ?internal oscillator pll disabled (see note 1) ?external clock pll disabled (see note 2) ?external clock pll enabled (see note 2) 75000 ? t c 25 ? t c 2500 ? t c ns ns ns 11 delay from asynchronous reset deassertion to first external address output (internal reset deassertion) 8 ? t c 9 ? t c + 20 ns 12 synchronous reset setup time from reset deassertion to ckout falling edge 8.5 t c ns 13 synchronous reset delay time from the ckout falling edge to the first external address output 8 ? t c 8 ? t c + 6 ns 14 mode select setup time 21 ns 15 mode select hold time 0 ns 16 minimum edge-triggered interrupt request assertion width 13 ns 16a minimum edge-triggered interrupt request deassertion width 13 ns 17 delay from irqa , irqb , nmi assertion to external memory access address out valid caused by first interrupt instruction fetch caused by first interrupt instruction execution 5 ? t c + t h 9 ? t c + t h ns ns 18 delay from irqa , irqb , nmi assertion to general purpose transfer output valid caused by first interrupt instruction execution 11 t c + t h ?s 19 delay from address output valid caused by first interrupt instruction execute to interrupt request deassertion for level sensitive fast interrupts (see note 3) ? t c + t l + (t c ws) - 23 ns 20 delay from rd assertion to interrupt request deassertion for level sensitive fast interrupts (see note 3) ?t c + (t c ws) - 21 ns 21 delay from wr assertion to interrupt request deassertion for level sensitive fast interrupts ws = 0 ws > 0 (see note 3) 2 t c - 21 t c + t l + (t c ws) - 21 ns ns reset, stop, mode select, and interrupt timing 28 dsp56005 data sheet motorola ac electrical characteristics notes: 1. a clock stabilization delay is required when using the on-chip crystal oscillator in two cases: ?after power-on reset, and ?when recovering from stop mode. during this stabilization period, t c , t h, and t l will not be constant. since this stabilization period varies, a delay of 75,000 ? t c is typically allowed to assure that the oscillator is stable before executing programs. 2. circuit stabilization delay is required during reset when using an external clock in two cases: ?after power-on reset, and ?when recovering from stop mode. 3. when using fast interrupts and irqa and irqb are defined as level-sensitive, then timings 19 through 22 apply to prevent multiple interrupt service. to avoid these timing restrictions, the deassertive edge-triggered mode is recommended when using fast interrupt. long interrupts are recommended when using level-sensitive mode. 22 delay from general-purpose output valid to interrupt request deassertion for level sensitive fast interrupts - if second interrupt instruction is: single cycle two cycles (see note 3) t l - 31 (2 t c ) + t l - 31 ns ns 23 synchronous interrupt setup time from irqa , irqb , nmi assertion to the ckout transition #2 10 t c ns 24 synchronous interrupt delay time from the ckout transition #2 to the first external address output valid caused by the first instruction fetch after coming out of wait state 13 t c + t h 13 t c + t h + 6 ns 25 duration for irqa assertion to recover from stop state 12 ns 26 delay from irqa assertion to fetch of first interrupt instruction (when exiting ?top? ?internal crystal oscillator clock, omr bit 6 = 0 ?stable external clock, omr bit 6 = 1 ?stable external clock, pctl bit 17 = 1 (see note 1) 65548 t c 20 t c 13 t c ns ns ns 27 duration of level sensitive irqa assertion to ensure inter- rupt service (when exiting ?top? ?internal crystal oscillator clock, omr bit 6 = 0 ?stable external clock, omr bit 6 = 1 ?stable external clock, pctl bit 17 = 1 (see note 1) 65534 t c + t l 6 t c + t l 12 ns ns ns 28 delay from level sensitive irqa assertion to fetch of first interrupt instruction (when exiting ?top? ?internal crystal oscillator clock, omr bit 6 = 0 ?stable external clock, omr bit 6 = 1 ?stable external clock, pctl bit 17= 1 (see note 1) 65548 t c 20 t c 13 t c ns ns ns table 12 reset, stop, mode select, and interrupt timing num characteristics 50 mhz unit min max reset, stop, mode select, and interrupt timing (continued) motorola dsp56005 data sheet 29 ac electrical characteristics figure 5 reset timing figure 6 synchronous reset timing figure 7 operating mode select timing v ihr reset a0-a15 first fetch 9 10 11 ckout reset a0-a15, ds , ps x/y 13 12 reset moda, modb modc irqa , irqb , nmi v ihm v ilm v ih v il 14 15 v ihr reset, stop, mode select, and interrupt timing 30 dsp56005 data sheet motorola ac electrical characteristics figure 8 external interrupt timing (negative edge-triggered) figure 9 external level-sensitive fast interrupt timing irqa , irqb nmi 16 irqa , irqb nmi 16a first interrupt instruction execution/fetch a0-a15 rd wr irqa irqb nmi 20 21 19 17 a) first interrupt instruction execution general purpose i/o irqa irqb nmi 18 22 b) general purpose i/o reset, stop, mode select, and interrupt timing motorola dsp56005 data sheet 31 ac electrical characteristics figure 10 synchronous interrupt from wait state timing figure 11 recovery from stop state using irqa figure 12 recovery from stop state using irqa interrupt service ckout irqa , irqb nmi a0-a15, ds ps , x/y 23 24 t0, t2 t1, t3 25 26 first instruction fetch irqa a0-a15, ds ps , x/y irqa a0-a15, ds ps , x/y first irqa interrupt instruction fetch 28 27 reset, stop, mode select, and interrupt timing 32 dsp56005 data sheet motorola ac electrical characteristics host i/o timing v cc = 5.0 vdc 10%, t j = -40 to +105 c, c l = 50 pf + 2 ttl load active low lines should be ?ulled up?in a manner consistent with the ac and dc speci? cations. table 13 host i/o timing num characteristics 50 mhz unit min max 31 hen /hack assertion width (see note 1) cvr, icr, isr, rxl read ivr, rxh/m read write t c + 31 26 13 ns 32 hen /hack deassertion width (see note 1) between two txl writes (see note 2) between two cvr, icr, isr, rxl reads (see note 3) 13 2 ? t c + 31 2 ? t c + 31 ns ns ns 33 host data input setup time before hen /hack deassertion 4 ns 34 host data input hold time after hen /hack deassertion 3 ns 35 hen /hack assertion to output data active from high impedance 0 ns 36 hen /hack assertion to output data valid 26 ns 37 hen /hack deassertion to output data high impedance (see note 5) ?8ns 38 output data hold time after hen /hack deassertion (see note 6) 2.5 ns 39 hr/w low setup time before hen assertion 0 ns 40 hr/w low hold time after hen deassertion 3 ns 41 hr/w high setup time to hen assertion 0 ns 42 hr/w high hold time after hen /hack deassertion 3 ns 43 ha0-ha2 setup time before hen assertion 0 ns 44 ha0-ha2 hold time after hen deassertion 3 ns 45 dma hack assertion to hreq deassertion (see note 4) 345ns host i/o timing motorola dsp56005 data sheet 33 ac electrical characteristics notes: 1. see host port use considerations in the design considerations section of this data sheet. 2. this timing must be adhered to only if two consecutive writes to the txl are executed without polling txde or hreq . 3. this timing must be adhered to only if two consecutive reads from one of these registers are executed without polling the corresponding status bits or hreq. 4. hreq is pulled up by a 1k w resistor. 5. specifications are periodically sampled and not 100% tested. 6. may decrease to 0 ns for future versions. 46 dma hack deassertion to hreq assertion (see notes 4, 5) for dma rxl read for dma txl write all other cases t l + t c + t h t l + t c 0 ns ns ns 47 delay from hen deassertion to hreq assertion for rxl read (see notes 4, 5) t l + t c + t h ?s 48 delay from hen deassertion to hreq assertion for txl write (see notes 4, 5) t l + t c ?s 49 delay from hen assertion to hreq deassertion for rxl read, txl write (see notes 4, 5) 358ns table 13 host i/o timing (continued) num characteristics 50 mhz unit min max host i/o timing 34 dsp56005 data sheet motorola ac electrical characteristics figure 13 host interrupt vector register (ivr) read hreq (output) hack (input) hr/w (input) h0-h7 (output) 32 42 37 36 35 38 data valid 41 31 host i/o timing motorola dsp56005 data sheet 35 ac electrical characteristics figure 14 host read cycle (non-dma mode) hreq (output) hen (input) ha2-ha0 (input) hr/w (input) h0-h7 (output) 47 49 31 32 43 44 41 42 36 37 35 38 rxm read rxl read address valid address valid address valid data valid data valid data valid rxh read host i/o timing 36 dsp56005 data sheet motorola ac electrical characteristics figure 15 host write cycle (non-dma mode) figure 16 host dma read cycle data valid data valid data valid 48 49 31 32 44 39 40 33 34 txm txl txh write address valid address valid address valid hreq (output) hen (input) ha2-ha0 (input) hr/w (input) h0-h7 (input) 43 35 31 32 45 46 46 36 37 38 data valid data valid data valid hreq (output) hack (input) h0-h7 (output) rxm read rxl read rxh read 46 host i/o timing motorola dsp56005 data sheet 37 ac electrical characteristics figure 17 host dma write cycle hreq (output) hack (input) h0-h7 (input) 31 32 45 46 46 33 34 data valid data valid data valid txm write txl write txh write host i/o timing 38 dsp56005 data sheet motorola ac electrical characteristics serial communication interface (sci) timing v cc = 5.0 vdc 10%, t j = -40 to +105 c, c l = 50 pf + 2 ttl load, tscc = synchronous clock cycle time (for internal clock, tscc is determined by the sci clock control register and t c ). the minimum tscc value is 8 t c . table 14 sci synchronous mode timing num characteristics 50 mhz unit min max 55 synchronous clock cycle ?tscc 8 t c ?s 56 clock low period tscc/2 - 10.5 ns 57 clock high period tscc/2 - 10.5 ns 58 < intentionally blank > 59 output data setup to clock falling edge (internal clock) tscc/4 + t l - 26 ns 60 output data hold after clock rising edge (internal clock) tscc/4 -t l - 8 ns 61 input data setup time before clock rising edge (internal clock) tscc/4 + t l + 23 ns 62 input data not valid before clock rising edge (internal clock) tscc/4 + t l - 5.5 ns 63 clock falling edge to output data valid (external clock) 32.5 ns 64 output data hold after clock rising edge (external clock) t c + 3 ns 65 input data setup time before clock rising edge (external clock) 16 ns 66 input data hold time after clock rising edge (external clock) 21 ns table 15 sci asynchronous mode timing ?1x clock num characteristics 50 mhz unit min max 67 asynchronous clock cycle - tacc 64 ? t c ?s 68 clock low period tacc/2 -11 ns 69 clock high period tacc/2 -11 ns 70 < intentionally blank > 71 output data setup to clock rising edge (internal clock) tacc/2 -51 ns 72 output data hold after clock rising edge (internal clock) tacc/2 -51 ns sci timing motorola dsp56005 data sheet 39 ac electrical characteristics figure 18 sci synchronous mode timing internal clock 56 57 55 60 59 62 61 data valid data valid external clock 56 57 55 64 63 66 65 data valid data valid sclk (output) txd rxd sclk (input) txd rxd sci timing 40 dsp56005 data sheet motorola ac electrical characteristics figure 19 sci asynchronous mode timing note : in the wire-or mode, txd can be pulled up by 1 k w 1x sclk (output) txd data valid 68 69 67 71 72 sci timing motorola dsp56005 data sheet 41 ac electrical characteristics synchronous serial interface (ssi) timing v cc = 5.0 vdc 10%, t j = -40 to +105 c l = 50 pf + 2 ttl load, tssicc = ssi clock cycle time txc (sck pin) = transmit clock rxc (sc0 or sck pin) = receive clock fst (sc2 pin) = transmit frame sync fsr (sc1 or sc2 pin) = receive frame sync i ck = internal clock x ck = external clock g ck = gated clock i ck a = internal clock, asynchronous mode (asynchronous implies that txc and rxc are two different clocks) i ck s = internal clock, synchronous mode (synchronous implies that txc and rxc are the same clock) bl = bit length wl = word length table 16 ssi timing num characteristics 50 mhz case unit min max 80 clock cycle-tssicc (see note 1) 4 ? t c 3 ? t c i ck x ck ns 81 clock high period t ssicc /2 - 10.8 t c + t l i ck x ck ns 82 clock low period t ssicc /2 - 10.8 t c + t l i ck x ck ns 83 < intentionally blank > 84 srd rising edge to fsr out (bl) high 40.8 25.8 x ck i ck a ns 85 srd rising edge to fsr out (bl) low 35.8 25.8 x ck i ck a ns 86 srd rising edge to fsr out (wl) high 35.8 20.8 x ck i ck a ns 87 rxc rising edge to fsr out (wl) low 35.8 20.8 x ck i ck a ns ssi timing 42 dsp56005 data sheet motorola ac electrical characteristics 88 data in setup time before rxc (sck in synchronous mode) falling edge 3.3 15.8 13 x ck i ck a i ck s ns 89 data in hold time after rxc falling edge 18 3.3 x ck i ck ns 90 fsr input (bl) high before rxc falling edge 0.8 17.4 x ck i ck a ns 91 fsr input (wl) high before rxc falling edge 3.3 18.3 x ck i ck a ns 92 fsr input hold time after rxc falling edge 18.3 3.3 x ck i ck ns 93 flags input setup before rxc falling edge 0.8 16.7 x ck i ck s ns 94 flags input hold time after rxc falling edge 18.3 3.3 x ck i ck s ns 95 txc rising edge to fst out (bl) high 31.6 15.8 x ck i ck ns 96 txc rising edge to fst out (bl) low 33.3 18.3 x ck i ck ns 97 txc rising edge to fst out (wl) high 30.8 18.3 x ck i ck ns 98 txc rising edge to fst out (wl) low 33.3 18.3 x ck i ck ns 99 txc rising edge to data out enable from high impedance 33.3 + t h 20.8 x ck i ck ns 100 txc rising edge to data out valid 33.3 + t h 22.4 x ck i ck ns 101 txc rising edge to data out high impedance (see note 2) 35.8 20.8 x ck i ck ns 101a txc falling edge to data out high impedance (see note 2) ? c + t h g ck ns 102 fst input (bl) setup time before txc falling edge 0.8 18.3 x ck i ck ns 103 fst input (wl) to data out enable from high impedance 30.8 ns table 16 ssi timing (continued) num characteristics 50 mhz case unit min max ssi timing motorola dsp56005 data sheet 43 ac electrical characteristics notes : 1. for internal clock, external clock cycle is defined by i cyc and ssi control register. 2. periodically sampled, and not 100% tested. 104 fst input (wl) setup time before txc falling edge 0.8 20.0 x ck i ck ns 105 fst input hold time after txc falling edge 18.3 3.3 x ck i ck ns 106 flag output valid after txc rising edge 32.5 20.8 x ck i ck ns table 16 ssi timing (continued) num characteristics 50 mhz case unit min max ssi timing 44 dsp56005 data sheet motorola ac electrical characteristics figure 20 ssi transmitter timing note: in the network mode, output flag transitions can occur at the start of each time slot within the frame. in the normal mode, the output flag state is asserted for the entire frame period. first bit last bit (see note) txc (input/output) fst (bit) out fst (word) out data out fst (bit) in fst (word) in flags out 81 82 80 95 96 97 98 100 100 99 105 102 103 104 105 106 101 101a ssi timing motorola dsp56005 data sheet 45 ac electrical characteristics figure 21 ssi receiver timing srd (input/output) fsr (bit) out fsr (word) out data in fsr (bit) in fsr (word) in flags in 81 82 84 85 86 87 88 89 first bit last bit 90 92 92 91 94 93 80 ssi timing 46 dsp56005 data sheet motorola ac electrical characteristics external bus asynchronous timing v cc = 5.0 vdc 10%, t j = -40 to +105 c, cl = 50 pf + 2 ttl load ws = number of wait states, determined by bcr register (ws = 0 to 15) capacitance derating the dsp56005 external bus timing speci?ations are designed and tested at the maximum ca- pacitive load of 50 pf, including stray capacitance. typically, the drive capability of the exter- nal bus pins (a0-a15, d0-d23, ps , ds , rd , wr , x/y , extp ) derates linearly at 1 ns per 12 pf of additional capacitance from 50 pf to 250 pf of loading. port b and c pins derate linearly at 1 ns per 5 pf of additional capacitance from 50 pf to 250 pf of loading. active low lines should be ?ulled up?in a manner consistent with the ac and dc speci?ations. table 17 external bus asynchronous timing num characteristics 50 mhz unit min max 120 address valid to wr assertion ws = 0 ws > 0 t l -6 t c -6 ns 121 wr assertion width ws = 0 ws > 0 t c ws x t c +t l ns 122 wr deassertion to address not valid t h -6 ns 123 wr assertion to data out active ws = 0 from high impedance ws > 0 t h -4 0 ns 124 data out hold time from wr deassertion (the maximum speci?ation is periodically sampled, and not 100% tested) t h -7 (see note 1) t h -2.5 (see note 2) ns 125 data out setup time to wr deassertion ws = 0 ws > 0 t l -0.8 ws x t c +t l -0.8 ns 126 rd deassertion to address not valid t h ?s 127 address valid to rd deassertion ws = 0 ws > 0 t c +t l -6 ((ws+1)x t c )+t l -6 ?s 128 input data hold time to rd deassertion 0 ns external bus asynchronous timing motorola dsp56005 data sheet 47 ac electrical characteristics notes: 1. wr deassertion to the end of valid data. 2. wr deassertion to data high impedance. 130 address valid to input data valid ws = 0 ws > 0 t c +t l -9.5 ((ws+1) x t c )+t l -9.5 ns 131 address valid to rd assertion tl-6 ns 132 rd assertion to input data valid ws = 0 ws > 0 t c -7.5 ((ws+1) x t c )- 7.5 ns 133 wr deassertion to rd assertion t c -7 ns 134 rd deassertion to rd assertion t c -4 ns 135 wr deassertion to wr assertion ws = 0 ws > 0 t c -4 t c +t h -4 ns ns 136 rd deassertion to wr assertion ws = 0 ws > 0 t c -4 t c +t h -4 ?s ns table 17 external bus asynchronous timing (continued) num characteristics 50 mhz unit min max external bus asynchronous timing 48 dsp56005 data sheet motorola ac electrical characteristics figure 22 external bus asynchronous timing note: during read-modify-write instructions, the address lines do not change state. a0-a15, ds , ps , x/y (see note) rd wr d0-d23 data out data in 120 135 121 122 133 131 129 127 126 134 123 136 128 125 130 132 124 external bus asynchronous timing motorola dsp56005 data sheet 49 ac electrical characteristics external bus synchronous timing v cc = 5.0 vdc 10%, t j = -40 to +105 c, c l = 50 pf + 2 ttl load capacitance derating the dsp56005 external bus timing speci?ations are designed and tested at the maximum ca- pacitive load of 50 pf, including stray capacitance. typically, the drive capability of the exter- nal bus pins (a0-a15, d0-d23, ps , ds , rd , wr , x/y , extp ) derates linearly at 1 ns per 12 pf of additional capacitance from 50 pf to 250 pf of loading. port b and c pins derate linearly at 1 ns per 5 pf of additional capacitance from 50 pf to 250 pf of loading. active low lines should be ?ulled up?in a manner consistent with the ac and dc speci?ations. notes: 1. ac timing specifications which are referenced to a device input signal are measured in production with respect to the 50% point of the respective input signal? transition. 2. ws are wait state values specified in the bcr. 3. ckout falling edge to data-out invalid (specification t146) and ckout falling edge to address invalid (specification t149) indicate the time after which data/address are no longer guaranteed to be valid. 4. timings are given from ckout midpoint to vol or voh of the corresponding pin(s). table 18 external bus synchronous timing num characteristics 50 mhz unit min max 140 ckout falling edge to address valid 6.2 ns 141 ckout rising edge to wr assertion ws=0 (see note 1) ws>0 4.4 t h +4.4 ns ns 142 ckout rising edge to wr deassertion 1.3 9.1 ns 143 ckout rising edge to rd assertion 3.9 ns 144 ckout rising edge to rd deassertion 0 3.4 ns 145 ckout falling edge to data-out valid 5.4 ns 146 ckout falling edge to data-out invalid (see note 3) 0 ns ns 147 data-in valid to ckout rising edge (setup) 3.4 ns 148 ckout rising edge to data-in invalid (hold) 0 ns 149 ckout falling edge to address invalid (see note 3) 0 ns 170 extal to ckout ?pll disabled extal to ckout ?pll enabled and mf < 5 3 0.3 9.7 3.7 ns ns external bus synchronous timing 50 dsp56005 data sheet motorola ac electrical characteristics figure 23 synchronous bus timing note: during read-modify-write instructions, the address lines do not change states. t0 t1 t2 t3 t0 t1 t2 t3 t0 ckout a0-a15 ds , ps extp , x/y rd wr d0-d23 extal data in data out 140 141 142 143 144 147 148 149 146 145 170 external bus synchronous timing motorola dsp56005 data sheet 51 ac electrical characteristics once tm port timing v cc = 5.0 vdc 10%, t j = -40 to +105 c, c l = 50 pf + 2 ttl loads table 19 once port timing num characteristics 50 mhz unit min max 230 dsck low 40 ns 231 dsck high 40 ns 232 dsck cycle time 200 ns 233 dr asserted to dso (a ck ) asserted 5t c ?s 234 dsck high to dso valid 42 ns 235 dsck high to dso invalid 3 ns 236 dsi valid to dsck low (setup) 15 ns 237 dsck low to dsi invalid (hold) 3 ns 238 last dsck low to os0-os1, a ck active 3t c + t l ?s 239 dso (a ck ) asserted to first dsck high 2t c ?s 240 dso (a ck ) assertion width 4t c + t h - 3 5t c + 7 ns 241 dso (a ck ) asserted to os0-os1 high impedance (see note 2) ?ns 242 os0-os1 valid to ckout rising edge t c - 21 ns 243 ckout rising edge to os0-os1 invalid 0 ns 244 last dsck low of read register to first dsck high of next command 7t c + 10 ns 245 last dsck low to dso invalid (hold) 3 ns 246 dr assertion to ckout rising edge for wake up from wait state 12 t c ns 247 ckout rising edge to dso after wake up from wait state 17t c ns 248 dr assertion width ?to recover from wait ?to recover from wait and enter debug mode 15 13t c +15 12t c - 15 ns 249 dr assertion to dso (a ck ) valid (enter debug mode) after asynchronous recovery from wait state 17t c ?s once port timing 52 dsp56005 data sheet motorola ac electrical characteristics notes: 1. a clock stabilization delay is required when using the on-chip crystal oscillator in two cases: ?after power-on reset ?when recovering from stop mode during this stabilization period, t c , t h, and t l will not be constant. since this stabilization period varies, a delay of 75,000 x t c is typically allowed to assure that the oscillator is stable before executing programs. while it is possible to set omr bit 6 = 1 when using the internal crystal oscillator, it is not recommended and these specifications do not guarantee timings for that case. 2. the maximum specified is periodically sampled and not 100% tested. 250a dr assertion width to recover from stop ?stable external clock, omr bit 6 = 0 ?stable external clock, omr bit 6 = 1 ?stable external clock, pctl bit 17= 1 (see note 1) 15 15 15 65548t c + t l 20t c + t l 13t c + t l ns 250b dr assertion width to recover from stop and enter debug mode ?stable external clock, omr bit 6 = 0 ?stable external clock, omr bit 6 = 1 ?stable external clock, pctl bit 17= 1 (see note 1) 65549t c + t l 21t c + t l 14t c + t l ns 251 dr assertion to dso (a ck ) valid (enter debug mode) after recovery from stop state ?stable external clock, omr bit 6 = 0 ?stable external clock, omr bit 6 = 1 ?stable external clock, pctl bit 17= 1 (see note 1) 65553t c + t l 25t c + t l 18t c + t l ns table 19 once port timing (continued) num characteristics 50 mhz unit min max once port timing motorola dsp56005 data sheet 53 ac electrical characteristics figure 24 once serial clock timing figure 25 once acknowledge timing figure 26 once data i/o to status timing dsck (input) 231 232 230 dr (input) 233 dso (output) (ack ) note: high impedance, external pull-down resistor dsck (input) dso (output) (ack ) (os1) dsi (input) 238 237 (os0) (see note) (last) 236 once port timing 54 dsp56005 data sheet motorola ac electrical characteristics figure 27 once read timing figure 28 once data i/o to status timing note: high impedance, external pull-down resistor dsck (input) dso (output) 245 (see note) (last) 235 234 note: high impedance, external pull-down resistor (dsck input) (dso output) (dsi input) os1 (output) dso (output) os0 (output) 236 241 240 (see note) 239 237 241 (see note) once port timing motorola dsp56005 data sheet 55 ac electrical characteristics figure 29 once ckout to status timing figure 30 once read register to next command timing figure 31 synchronous recovery from wait state note: high impedance, external pull-down resistor ckout os0-os1 (output) 243 242 (see note) dsck (input) 244 (next command) ckout dr (input) dso (output) 246 247 t0, t2 t1, t3 248 once port timing 56 dsp56005 data sheet motorola ac electrical characteristics figure 32 asynchronous recovery from wait state figure 33 asynchronous recovery from wait state dr (input) dso (output) 249 248 dr (input) dso (output) 251 250 once port timing motorola dsp56005 data sheet 57 ac electrical characteristics timer timing v cc = 5.0 vdc 10%, t j = -40 to +105 c, c l = 50 pf + 2 ttl loads figure 34 tio timer/ event input restrictions table 20 timer timing num characteristics 50 mhz unit min max 260 tio low 2t c +7 ns 261 tio high 2t c +7 ns 262 synchronous timer setup time from tio (input) asssertion to ckout rising edge 10 t c ns 263 synchronous timer delay time from ckout rising edge to the external memory access address out valid caused by first interrupt instruction execution 5t c +t h ?s 264 ckout rising edge to tio (output) assertion 0 8 ns 265 ckout rising edge to tio (output) deassertion 0 8 ns 266 ckout rising edge to tio (general purpose output) 0 8 ns tio 261 260 timer timing 58 dsp56005 data sheet motorola ac electrical characteristics figure 35 timer interrupt generation figure 36 external pulse generation figure 37 gpio output timing ckout tio (input) first interrupt instruction execution address 262 263 ckout tio ( output ) 264 265 ckout t io (output) a0-a15 fetch the instruction move x0,x:(r0) ; x0 contains the new value of tio ; and r0 contains the address of tcsr ps ,ds x/y extp , 266 timer timing motorola dsp56005 data sheet 59 ac electrical characteristics pulse width modulator (pwm) timing v cc = 5.0 vdc 10%, t j = -40 to +105 c, c l = 50 pf + 2 ttl load wps = pwm prescale factor wcn = pwm count ick = internal clock xck = external clock note: if wcn=0 then the output is not asserted at all. table 21 pwm timing num characteristics 50 mhz case unit min max 280 pwm external clock low (t wl ) t c + 3 ns 281 pwm external clock high (t wh ) t c + 3 ns 282 pwm external clock cycle (t wc ) 2 x t c + 6 ns 283 pwm external carrier low 2 x t c + 3 x wps x t c + 14 3 x t c + t wc + t wl +14 3 x t c + 1.5 x wps x t wc + 14 ick xck wps = 1 xck wps > 1 ns 284 pwm external carrier high 15 ns 285 pwm clock rising edge to pwm output assertion 2 x t c +t l +35 ns 286 pwm carrier rising edge to pwm output assertion 3 x t c 3 x t c 3 x t c 2 x t c + 3 x wps x t c + 35 3 x t c + t wc + t wl + 35 3 x t c + 1.5 x wps x t wc + 35 ick xck wps = 1 xck wps > 1 ns 287 pwm clock rising edge to pwm output deasser- tion 2 x t c + t l + 35 ns ns 288 pwm output assertion time (see note) 2 x wcn x wps x t c - 3 wcn x wps x t wc - t c - 3 2 x wcn x wps x t c + 3 wcn x wps x twc + t c + 3 ick xck ns 289 synchronous pwm ris- ing edge clock setup time to ckout falling edge 12 t c - 3 ns 290 synchronous pwm car- rier setup time to ckout rising edge 14 t c - 2 ns 291 ckout rising edge to pwm output assertion for synchronous operation 2 x t c +wps ? t c + 3 2 x t c + t wl + 3 2 x t c + .5 x wps x t wc + 3 t c + 3 x wps x t c + 26 t c + t wc + t wl + 26 t c + 1.5 x wps x t wc + 26 ick xck wps = 1 xck wps > 1 ns 292 pwm output assertion time in synchronous operation wcn x wps x t wc - 3 wcn x wps x t wc + 3 ns ns pwm timing 60 dsp56005 data sheet motorola electrical characteristics figure 38 pwm clock input restrictions figure 39 pwm carrier input restrictions figure 40 pwm output asynchronous operation pwaclk 280 281 pwbclk 282 pwacn pwbc 283 284 pwaclk pwbclk pwbc pwacn pwbm pwapn 286 285 287 288 pwm timing motorola dsp56005 data sheet 61 electrical characteristics figure 41 pwm output synchronous operation pwaclk pwbclk pwbc pwacn pwbm pwapn ckout 289 290 291 292 pwm timing 62 dsp56005 data sheet motorola pin-out and package pin-out and package information top and bottom views of the thin quad flat package (tqfp) are shown in figure 42 and figure 43 with their pin-outs. figure 42 top view of the dsp56005 144-pin plastic thin quad flat package (tqfp) a15 a14 gnda a13 v cca a12 a11 a10 gnda a9 a8 a7 a6 gnda v cca a5 gndq v ccq a4 a3 a2 gnda a1 a0 ps v cca ds gnda x/y extp dsi/os0 dso dr gndc dsck/os1 v ccc (top view) modc/nmi modb/irqb moda/irqa gndck ckout vccck reset pinit vccp pcap gndp xtal extal ha2/pb10 gndh vccq gndq ha1/pb9 ha0/pb8 ha ck /pb14 vcch hen /pb12 gndh hr/w /pb11 hreq /pb13 h7/pb7 h6/pb6 gndh h5/pb5 h4/pb4 h3/pb3 vcch h2/pb2 gndh h1/pb1 h0/pb0 orientation mark 109 1 37 73 wr rd srd/pc7 sc1/pc4 gnds std/pc8 sc2/pc5 sck/pc6 v ccs sc0/pc3 txd/pc1 gnds rxd/pc0 sclk/pc2 tio pwap0 pwan0 v ccq gndq pwac0 gndw pwap1 pwan1 pwac1 v ccw pwap2 pwan2 pwac2 gndw pwaclk pwb0 pwb1 pwbc pwbclk irqc nc d0 d1 gndd d2 d3 v ccd d4 d5 gndd d6 d7 d8 d9 gndd d10 d11 v ccd d12 d13 gndd v ccq gndq d14 d15 d16 d17 gndd d18 d19 v ccd d20 d21 gndd d22 d23 irqd notes: 1. ?c are no connection pins that are reserved for possible future enhancements. do not con- nect these pins to any power, ground, signal traces, or vias. 2. an o verbar indicates the signal is asserted when the voltage = ground (active low). 3. to simplify locating the pins, each ?th pin is shaded in the illustration. 144-pin tqfp top view pin-out and package motorola dsp56005 data sheet 63 pin-out and package figure 43 bottom view of the dsp56005 144-pin plastic thin quad flat package (tqfp) (bottom view) a15 a14 gnda a13 v cca a12 a11 a10 gnda a9 a8 a7 a6 gnda v cca a5 gndq v ccq a4 a3 a2 gnda a1 a0 ps v cca ds gnda x/y extp dsi/os0 dso dr gndc dsck/os 1 v ccc modc/nmi modb/irqb moda/irqa gndck ckout v ccck reset pinit v ccp pcap gndp xtal extal ha2/pb10 gndh v ccq gndq ha1/pb9 ha0/pb8 ha ck /pb14 v cch hen /pb12 gndh hr/w /pb11 hreq /pb13 h7/pb7 h6/pb6 gndh h5/pb5 h4/pb4 h3/pb3 v cch h2/pb2 gndh h1/pb1 h0/pb0 orientation mark 109 1 37 73 nc irqc pwbclk pwbc pwb1 pwb0 pwaclk gndw pwac2 pwan2 pwap2 v ccw pwac1 pwan1 pwap1 gndw pwac0 gndq v ccq pwan0 pwap0 tio sclk/pc2 rxd/pc0 gnds txd/pc1 sc0/pc3 v ccs sck/pc6 sc2/pc5 std/pc8 gnds sc1/pc4 srd/pc7 rd wr irqd d23 d22 gndd d21 d20 v ccd d19 d18 gndd d17 d16 d15 d14 gndq v ccq gndd d13 d12 v ccd d11 d10 gndd d9 d8 d7 d6 gndd d5 d4 v ccd d3 d2 gndd d1 d0 (on top side) notes: 4. ?c are no connection pins that are reserved for possible future enhancements. do not con- nect these pins to any power, ground, signal traces, or vias. 5. an o verbar indicates the signal is asserted when the voltage = ground (active low). 6. to simplify locating the pins, each ?th pin is shaded in the illustration. 144-pin tqfp bottom view 64 dsp56005 data sheet motorola pin-out and package figure 44 dsp56005 144-pin tqfp shipping tray 5 x 12 top view orientation marks shipping tray motorola dsp56005 data sheet 65 pin-out and package by general purpose i/o 66 dsp56005 data sheet motorola pin-out and package by pin number motorola dsp56005 data sheet 67 pin-out and package by pin number 68 dsp56005 data sheet motorola pin-out and package by pin number motorola dsp56005 data sheet 69 pin-out and package by signal name 70 dsp56005 data sheet motorola pin-out and package by signal name motorola dsp56005 data sheet 71 pin-out and package by signal name 72 dsp56005 data sheet motorola pin-out and package by signal name motorola dsp56005 data sheet 73 pin-out and package power supply pins 74 dsp56005 data sheet motorola pin-out and package power supply pins motorola dsp56005 data sheet 75 pin-out and package 76 dsp56005 data sheet motorola pin-out and package motorola dsp56005 data sheet 77 pin-out and package table 25 dsp56005 power supply pins "005pv" 144-pin tqfp pin power supply circuit supplied 113 v cca address bus buffers 123 134 111 gnda 117 122 130 136 144 v ccc bus control buffers 142 gndc 67 v ccck clock 69 gndck 79 v ccd data bus buffers 92 103 76 gndd 82 89 95 100 106 78 dsp56005 data sheet motorola pin-out and package 41 v cch host interface buffers 52 39 gndh 45 50 58 18 v ccq internal logic 57 88 126 19 gndq 56 87 125 64 v ccp pll 62 gndp 25 v ccw pulse width modulator 21 gndw 29 9v ccs serial port 5 gnds 12 table 25 dsp56005 power supply pins (continued) "005pv" 144-pin tqfp pin power supply circuit supplied motorola dsp56005 data sheet 79 pin-out and package 80 dsp56005 data sheet motorola pin-out and package ss m 0.102 (0.004) seating plane -t- t l- m n m s s s 0.204 (0.008) t l- m n s 0.508 (0.020) t l- m n m s s s 0.508 (0.020) t l- m n m s s s 0.204 (0.008) s a pin 1 ident ec w 144 109 108 73 1 36 37 72 view p -h- b v view y g 140 pl plating f j d base metal b1 section j1-j1 144 pl (rotated 90?) 0.13 (0.005) tl -m s n s m notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane -h- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums -l-, -m- and -n- to be determined at datum plane -h-. 5. dimensions s and v to be determined at seating plane -t-. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane -h-. min min max max millimeters inches dim a b c d e f g j k s v w z a1 b1 c1 r1 r2 ? 1 ? 2 19.900 19.900 1.400 0.170 1.350 0.160 0.130 0.450 21.900 21.900 0.050 0.100 0.100 0.150 05 05 20.100 20.100 1.600 0.280 1.450 0.270 0.180 0.750 22.100 22.100 0.150 0.150 0.250 85 85 0.783 0.783 0.056 0.0067 0.054 0.063 0.005 0.018 0.863 0.863 0.002 0.004 0.004 0.006 0 5 05 0.791 0.791 0.062 0.0110 0.057 0.011 0.007 0.029 0.870 0.870 0.006 0.006 0.010 85 85 0.500 bsc 0.197 bsc 0.250 bsc 0.0098 bsc 1.000 ref 0.039 ref 0.150 ref 0.006 ref 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the ddimension at maximum material condition. -l-, -m-, -n- view y 3 pl j1 j1 z -h- view p a1 r1 r2 12? 2 pl seating plane c1 ? 1 ? 2 k motorola dsp56005 data sheet 81 pin-out and package figure 45 dsp56005 144-pin tqfp mechanical information motorola dsp56005 data sheet 77 design considerations design considerations heat dissipation the average chip junction temperature, t j , in c, can be obtained from: t j = t a + (p d ? q ja ) (1) where: t a = ambient temperature, c q ja = package thermal resistance, junction-to-ambient, c/w p d =p int + p i/o p int =i cc v cc watts ?chip internal power p i/o = power dissipation on input and output pins ?user determined for most applications p i/o < p int and p i/o can be neglected. an appropriate relationship be- tween p d and t j (if p i/o is neglected) is: p d = k/(t j + 273) (2) solving equations (1) and (2) for k gives: k = p d ? (t a + 273) + p d q ja (3) where: k is a constant pertaining to the particular package k can be determined from equation (2) by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a . the to- tal thermal resistance of a package ( q ja ) can be separated into two components, q jc and q ca , representing the barrier to heat flow from the semiconductor junction to the package (case) surface ( q jc ) and from the case to the outside ambient ( q ca ). these terms are related by the equation: q ja = q jc + q ca (4) q jc is device-related and cannot be influenced by the user. however, q ca is user-dependent and can be minimized by thermal manage- ment techniques such as heat sinks, ambient air cooling, and thermal convection. thus, good thermal management can signi?antly reduce q ca so that q ja approximately equals q jc . values for thermal resistance presented in this document, unless estimated, were de- rived using the procedure described in mo- torola reliability report 7843, ?hermal resistance measurement method for mc68xx microcomponent devices? and are provided for design purposes only. thermal measurements are complex and dependent on procedure and setup. user-derived values for thermal resistance may differ. note : table 7, ?hermal characteristics of the tqfp package,?on page 21 contains the package thermal val- ues for this chip. heat dissipation 78 dsp56005 data sheet motorola design considerations power, ground, and noise each dsp56005 v cc pin should be provided with a low-impedance path to the board? supply. each dsp56005 gnd pin should also be provided with a low-impedance path to ground. the power supply pins drive dis- tinct groups of logic on chip as shown in table 25, ?sp56005 power supply pins,?on page 77. the v cc power supply should be by- passed to gnd using at least four 0.1 m f by-pass capacitors located as close as possi- ble to the four sides of the package. the ca- pacitor leads and associated printed circuit traces connecting to chip v cc and gnd should be less than 0.5?per capacitor lead. a four-layer board is recommended, employ- ing two inner layers as v cc and gnd planes. all output pins on this dsp have fast rise and fall times. printed circuit board (pcb) trace lengths should be minimal. this recommen- dation particularly applies to the address and data buses as well as the rd , wr , irqa , irqb , irqc , irqd , nmi , hen, and hack pins. capacitance calculations should con- sider all device loads as well as parasitic ca- pacitances due to the pcb traces. attention to proper pcb layout and bypassing becomes especially critical in systems with higher ca- pacitive loads because these loads create higher transient currents in the v cc and gnd circuits. pull up all unused inputs or signals that will be inputs during reset. spe- cial care should be taken to minimize the noise levels on the pll supply pins. power consumption power dissipation is a key issue in portable dsp applications. this section describes some factors which affect current consumption. this current consumption is described by the formula: i=c v f where: c = node/pin capacitance v = voltage swing f = frequency of node/pin toggle for example, for a port a address pin loaded with a 50 pf capacitance and operating at 5.5v with a 40 mhz clock, toggling at its maximum possible rate (which is 10 mhz), the current consumption is: i=50 ? 10 -12 ? 5.5 10 10 6 = 2.75 ma the maximum internal current value (i cci -max), re?cts the maximum possible switching of the internal buses, which is not necessarily a real application case. the typi- cal internal current value (i cci -typ) re?cts the average switching of the internal buses. the following steps are recommended for ap- plications requiring very low current con- sumption: 1. minimize external memory accesses; use internal memory accesses instead 2. minimize the number of pins which are switching 3. minimize the capacitive load on the pins 4. connect the unused inputs to pull-up or pull-down resistors power consumption power, ground, and noise motorola dsp56005 data sheet 79 design considerations current consumption test code: org p:reset jmp main org p:main movep #$180000,x:$fffd move #0,r0 move #0,r4 move #$00ff,m0 move #$00ff,m4 nop rep #256 move r0,x:(r0)+ rep #256 mov r4,y:(r4)+ clr a move l:(r0)+,a rep #30 mac x0,y0,a x:(r0)+,x0 y:(r4)+,y0 move a,p:(r5) jmp tp1 tp1 nop jmp main host port considerations careful synchronization is required when reading multi-bit registers that are written by another asynchronous system. this is a com- mon problem when two asynchronous sys- tems are connected. the situation exists in the host interface. the following paragraphs present considerations for proper operation. host programming considerations 1. unsynchronized reading of receive byte registers when reading receive byte registers, rxh or rxl, the host program should use interrupts or poll the rxdf ?g which indicates that data is available. this assures that the data in the receive byte registers will be stable. 2. overwriting transmit byte registers the host program should not write to the transmit byte registers, txh or txl, un- less the txde bit is set, indicating that the transmit byte registers are empty. this guarantees that the transmit byte registers will transfer valid data to the hrx register. 3. synchronization of status bits from dsp to host hc, hreq, dma, hf3, hf2, trdy, txde, and rxdf status bits are set or cleared from inside the dsp and read by the host processor (refer to dsp56005 us- er s manual for descriptions of these sta- tus bits). the host can read these status bits very quickly without regard to the clock rate used by the dsp, but the state of the bit could be changing during the read operation. generally, this is not a system problem, since the bit will be read correct- ly in the next pass of any host polling rou- tine. however, if the host asserts hen for more than timing number 31 , with a mini- mum cycle time of timing number 31 + 32 , then these status bits are guaran- teed to be stable. exercise care when reading status bits hf3 and hf2 as an encoded pair. if the dsp changes hf3 and hf2 from 00 to 11, there is a small probability that the host could read the bits during the transition and receive 01 or 10 instead of 11. if the combination of hf3 and hf2 has signi?ance, the host could read the wrong combination. therefore, read the bits twice and check for consensus. 4. overwriting the host vector the host program should change the host vector register only when the host command bit (hc) is clear. this change will guarantee that the dsp interrupt control logic will receive a stable vector. host programming considerations 80 dsp56005 data sheet motorola design considerations 5. cancelling a pending host command exception the host processor may elect to clear the hc bit to cancel the host command exception request at any time before it is recognized by the dsp. because the host does not know exactly when the exception will be recognized (due to exception processing synchronization and pipeline delays), the dsp may exe- cute the host command exception after the hc bit is cleared. for these reasons, the hv bits must not be changed at the same time that the hc bit is cleared. 6. variance in the host interface timing the host interface (hi) may vary (e.g. due to the pll lock time at reset). therefore, a host which attempts to load (bootstrap) the dsp56005 should ?st make sure that the part has com- pleted its hi port programming (e.g. by setting the init bit in icr then polling it and waiting it to be cleared, then reading the isr or by writing the treq/rreq together with the init and then polling init, isr, and the hreq pin). dsp programming considerations 1. synchronization of status bits from host to dsp dma, hf1, hf0, and hcp, htde, and hrdf status bits are set or cleared by the host processor side of the interface. these bits are individu- ally synchronized to the dsp clock. (refer to the dsp56005 user s manual for descriptions of these status bits.) 2. reading hf0 and hf1 as an encoded pair care must be exercised when reading status bits hf0 and hf1 as an encoded pair, i.e., the four combinations 00, 01, 10, and 11 each have signi?ance. a very small probability exists that the dsp will read the status bits synchro- nized during transition. therefore, hf0 and hf1 should be read twice and checked for consensus. dsp programming considerations host programming considerations motorola dsp56005 data sheet 81 design considerations application examples the lowest cost dsp56005 based system is shown in figure 46. it uses no run time external memory and requires only two chips, the dsp56005 and a low cost eprom. the eprom read access time should be less than 300 nanoseconds when the dsp56005 is operating at a clock rate of 50 mhz. figure 46 no glue logic, low cost memory port bootstrap ?mode 1 11 8 ce a0-a10 d0-d7 2716 mbd301* +5 v from open collector buffer from reset function from open collector buffer mbd301* dsp56005 ps a0-a10 d0-d7 moda/irqa reset modb/irqb hack modc/nmi dr notes: 1. * these diodes must be schottky diodes. 2. all resistors are 15 k w unless noted otherwise. 3. when in reset, irqa , irqb , and nmi must be deasserted by external peripherals. pinit application examples 82 dsp56005 data sheet motorola design considerations a system with external data ram memory requires no glue logic to select the external eprom from bootstrap mode. ps is used to enable the eprom and ds is used to enable the high speed data memories as shown in figure 47. figure 47 port a bootstrap with external data ram ?mode 1 moda/irqa reset modb/irqb 24 8 mbd301* +5 v from open collector buffer from reset function from open collector buffer a0-a10 d0-d7 a0-a9 a10 cs we oe rd ps x/y wr ce a0-a10 2716 d0-d23 11 10 2018 (3) d0-d23 hack mbd301* modc/nmi dr dsp56005 notes: 1. * these diodes must be schottky diodes. 2. all resistors are 15 k w unless noted otherwise. 3. when in reset, irqa , irqb , and nmi must be deasserted by external peripherals. pinit application examples motorola dsp56005 data sheet 83 design considerations figure 48 shows the dsp56005 bootstrapping via the host port from an mc68000. figure 48 dsp56005 host bootstrap example ?mode 5 mc68000 (12.5 mhz) dsp56005 hr/w hen h0-h7 f32 f32 f32 f32 address decode 1k +5 v ha0-ha2 lds as dtack a1-a3 d0-d7 r/w a4-a23 8 3 moda/irqa reset modb/irqb mbd301* +5 v from open collector buffer from reset function from open collector buffer hack modc/nmi dr ls09 notes: 1. * these diodes must be schottky diodes. 2. all resistors are 15 k w unless noted otherwise. 3. when in reset, irqa , irqb , and nmi must be deasserted by external peripherals. pinit application examples 84 dsp56005 data sheet motorola design considerations in figure 49, the dsp56005 is operated in mode 3 with external program memory at location $e000. the programmer can overlay the high speed on-chip p:ram with dsp algorithms by using the movem instruction. figure 49 32k words of external program rom ?mode 3 dsp56005 24 a0-a14 a0-a14 cs oe rd ps d0-d23 15 moda/irqa reset modb/irqb +5 v from open collector buffer from reset function from open collector buffer hack mbd301* modc/nmi dr 2756 (3) d0-d23 notes: 1. * these diodes must be schottky diodes. 2. all resistors are 15 k w unless noted otherwise. 3. when in reset, irqa , irqb , and nmi must be deasserted by external peripherals. pinit application examples motorola dsp56005 data sheet 85 design considerations figure 50 shows a circuit which waits until v cc on the dsp56005 is at least 4.5 v before initi- ating a 75,000 ? t c oscillator stabilization delay required for the on-chip oscillator (only 25 t c is required for an external oscillator without the pll or 2500 t c for an external oscillator with the pll enabled). this insures that the dsp is operational and stable before releasing the reset signal. figure 50 reset circuit using mc34064/mc33064 notes: 1. irqa , irqb , and nmi must be driven to the logic levels appropriate for the application. 2. moda, modb, and modc must be driven to the logic levels appropriate for the application. reset 1.2 v ref + - +5v mc34064 u1 mc33064 2 (2) 3 (4) 1 (1) c dly r t dly = rc dly in 1 1 - v th v in - v ol where: logic reset t dly = 75,000 t c minimum v in = 5 v f osc = 20 mhz v th = 2.5 v v ol = 0.4 v c dly = 1 m f 20% t c = 50 ns r = 8.2 k 5% application examples 86 dsp56005 data sheet motorola design considerations figure 51 shows the dsp56005 connected to the bus of an ibm-pc computer. this circuit is complete and does not require external rom or ram to load and execute code from the pc. the pal equations and other details of this circuit are available in the application note enti- tled ?sp56001 interface techniques and examples?(arp11/d). figure 51 dsp56005 -to- isa bus interface schematic ha0 ha1 ha2 hen hr/w moda/irqa modb/irqb reset hreq hack 14 d01 d02 d03 d04 d05 d06 a02 a01 a00 d07 10 12 121 120 8 125 21 23 13 13 d00 a09 a08 a07 a06 a05 a04 a03 a02 a31 a30 a29 1 5 14 2 6 16 22 8 4 17 7 3 9 osc a04 a05 a06 a07 a08 a09 a14 a17 a22 a23 a24 a25 a26 a27 b30 mc74act245 pal22v10 h7 h6 h5 h4 h3 h2 h1 h0 10 11 aen ior iow b13 b14 a11 15 dsp56005 15 18 17 19 21 23 24 9 8 6 7 5 4 3 2 7 6 4 11 12 14 13 15 16 17 18 19 1 oe dir irqb irqa modc/nmi 119 dr 51 note: connector is j1 of isa bus all series resistors are 15 k ohms external interrupt sources pinit +5v application examples motorola dsp56005 data sheet 87 ordering information ordering information table 26 lists the pertinent information needed to place an order. consult a motorola semi- conductor sales of?e or authorized distributor to determine availability and to order parts. table 26 dsp56005 ordering information part supply voltage package type pin count frequency (mhz) order number dsp56005 5 v plastic thin quad flat pack (tqfp) 144 50 dsp56005pv50 literature distribution centers usa/europe: motorola literature distribution; p.o. box 20912; phoenix, arizona 85036 usa japan: nippon motorola ltd.; 4-32-1, nishi-gotanda, shinagawa-ku, tokyo 141 japan. asia-pacific: motorola semiconductors h.k. ltd.; silicon harbor center, no. 2 dai king street, tai po industrial estate, tai po, n.t., hong kong. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, repre- sentation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limi- tation consequential or incidental damages. ?ypical?parameters can and do vary in different applications. all operating param- eters, including ?ypical? must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and b are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af?mative action employer. once is a trademark of motorola, inc. |
Price & Availability of DSP56005DS
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |